Digital Circuits Testing Based on Pattern Overlapping and Broadcasting

and contributions The high test data volume and long test application time are two major concerns for testing scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction. This dissertation thesis presents a new test compression and test application approach that combines both the test pattern overlapping technique and the test pattern broadcasting technique. It presents a novel on-chip broadcast-based test decompressor architecture that utilizes these two techniques. Test compression algorithm and architecture configuration heuristics are presented as well. This dissertation thesis will illustrate that these new techniques are effective in both the test application time and the test data volume reduction with low hardware area overhead. The proposed methodologies are verified by simulations and through experiments. In particular, the main contributions of the dissertation thesis are as follows: 1. New on-chip test decompressor architecture utilizing broadcasting and overlapping test pattern decompression techniques 2. New test set compression method suitable for the novel decompressor architecture 3. Scan chain configuration method suitable for the novel decompressor architecture